State- machine is used to implement the timing logic in CPLD, and the main codes written by VHDL language are given.
CPLD的接口时序逻辑控制功能采用状态机工作方式实现,并给出了用VHDL编写的主要源代码。
Doppler frequency drift and timing error were considered in state transform equations.
状态方程综合考虑了多普勒频移、定时误差。
Because of differences in goals, methods and timing, these state capital joint stock companies had a far from consistent effect on socioeconomic life.
由于目的、方式及时期的不同,这些国家资本股份制企业在社会经济生活中发挥的作用也并非一致。
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