This paper described the mode and implementation of the new algorithm architecture.
论文分析了算法框架的实现和优化的分析流程与模型实现。
The pipelined implementation shows that the new algorithm occupies about 1/16 of the old one.
采用流水线结构的硬件实现表明，新算法占用的资源大约为原来的1/16。
A new ASIC implementation of RSA algorithm is presented. It has less area and more flexibility, making the chip very suitable for smart card applications.
提出了一种实现RSA算法的新型ASIC结构，具有较小的芯片面积和较强的灵活性，适合于智能IC卡应用。
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