Yield of the redundant circuit is analyzed with IC critical area and the computational model of this redundant circuit is given.
利用关键面积的思想分析了冗余电路的成品率，并给出了其计算模型。
The influence on over etching and under etching to IC layout is analyzed, the computation model and realization method of IC critical area are presented.
论文在分析过刻蚀和欠刻蚀对IC版图影响的基础上，提出了基于工艺偏差影响的IC关键面积计算新模型和实现方法。
It is important to the calculation of VLSI critical area and the optimization of IC layout design.
这对计算VL SI关键面积、指导版图优化设计和提高IC成品率有重要意义。
应用推荐