The serial digital high definition video signal will be used as an input source for high definition encoder and generate high definition video programs.
该串行数字高清视频信号将作为高清编码器的输入源，可以用于完成高清数字视频节目的制作。
The VLSI architecture is regular, and video signal processing speed is very high, because of the regularity of the proposed algorithm.
算法的规则性决定了对应的VLSI结构的规则性、紧凑性和视频信号处理的高速度。
The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal.
视频介绍上的并行lvcmos总线串行数据序列化为一个高速差分信号。
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