Internal high-speed clock trimming 内部高速时钟调整
External high-speed clock enable 外部高速时钟使能
Internal high-speed clock calibration 内部高速时钟校准
high-speed clock circuit 高速时钟电路
high speed clock circuit 高速时钟电路
External high-speed clock bypass 外部高速时钟旁路
The paper presents a square wave modulation scheme based on TDMA signal system to resolve the problem. Also it can avoid the high speed system clock.
该文提出了一种基于TDMA信号体制下的方波调制方案，该方案既解决了远近效应，又避免了在较高的中频上采用过高的系统时钟。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
The system based on the frequency synthesizer can offer a high accuracy, high stability and low jitter clock for a high speed and high precision backplane test platform.
该时钟板基于频率合成器来产生高精度、高稳定度、低抖动的时钟，用于高速高精度背板测试平台。
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