In this paper, the VHDL high level abstract model is outlined, and the language basics in VHDL which can be used to support and represent this model are introduced.
本文概述了VHDL的高级抽象模型，并对VHDL中支持和表示此模型的语言基础作了简介。
Ganesh points out that "the" canonical data model is typically too high-level and abstract for the practical use.
Ganesh指出所谓规范的数据模型通常层次较高且对于实践应用来说过于抽象。
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