... conventional gate level simulation 惯用闸位准模拟 Gate Level Design 完成逻辑闸层次设计 Gate Level logic Design 闸口逻辑设计 ...
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The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
Using gate level modeling might not be a good idea for any level of logic design.
使用门级建模对于任何逻辑设计都不是一个好的设计。
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