大学类标准元 件数位电路设计组（D组）初赛时需完成逻辑闸层次设计（Gate Level Design），决赛时 亦以完成逻辑闸层次设计（Gate Level Design）视为完成比赛，但完成实体阶层设计 （Physical Design）者可获得额外加分...
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Gate Level logic Design 闸口逻辑设计
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.
这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。
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