gate level synthesis 门级综合
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。
Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping.
高级综合结果中常量元件和输出悬空端口导致门级工艺映射结果中存在显式冗余。
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