According to the theory in video compression as well as the simulation and verification requirement in IP core designing, the FPGA based IP core simulation platform is developed.

结合视频压缩的理论以及IP核设计中对于仿真验证的要求，本文设计了视频压缩IP核FPGA仿真验证平台。

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Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.

最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。

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