All circuits are designed by HDL and can be intergrated in one CPLD or FPGA chip, used in the frame synchronization and timing of digital communications receiver.

全部电路由硬件描述语言实现，可以集成在一片CPLD或FPGA芯片内部，用于数字通信系统接收端的帧同步和定时。

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In order to improve digital signal processing speed, dedicated algorithm to achieve some of the DSP and communication interface module also realized by the CPLD or FPGA.

为了提高数字信号处理速度，现在一些实现专用算法的DSP模块和通信接口也由FPGA或者CPLD实现。

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The article introduces a unique hardware realization, which utilizes less-foot, low-cost and easy-to-get logistic interfaces, as PAL, CPLD or FPGA.

本文介绍了一种特殊的硬件实现方法，使用了管脚少、成本低、容易得到的逻辑接口器件，例如可编程逻辑阵列（PAL）、可编程逻辑电路（CPLD）或者FPGA。

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