A double edge triggered counter is designed, and the redundancy attribute of the circuit is utilized to decrease the power consumption of the system.
设计了双边沿触发计数器，并利用电路的冗余特性，降低了系统的功耗。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
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