This paper explores the methods for improving circuit design with VHDL.

本文探讨了VHDL电路设计的优化方法。

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Based on a classical example, we specify how. to begin a Top -down design with VHDL. Also, we point out that how to incorporate VHDL into a being used EDA environment.

结合一个典型例子，说明如何采用VHDL开始一个自顶向下的设计，指出如何在现有的环境中有效开发VHDL的应用。

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The design of source files by VHDL, compilation and synthesis, and implementation methods with HDPLD are discussed.

着重讨论了用VHDL设计源文件，通过综合编译，用HDPLD实现的方法。

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