Programmable delay chip 可编程延迟芯片
on-chip delay 片上延迟
chip delay line 芯片延迟线
on chip delay 片上延迟
Single Chip Digital Delay 单芯片数字延迟
NOC is a kind of flexible and scalable micro-network on chip, of which the main guild lines are network throughput, delay, resource consumption and power consumption.
NOC是一个弹性的、可扩展的芯片微网络，网络的吞吐率、延迟、资源耗费以及功耗是片上网络重要的性能指标。
The algorithm of CPLD chip designed in this paper, using two pulse-counting and CPLD hardware delay means to achieve the balance between CPLD resource consumption and function.
本文设计的CPLD芯片的算法，采用两级脉冲计数及CPLD硬件延时方法，以达到CPLD资源占用和功能实现的平衡。
FPGA placement and routing is the most time-consuming stage in chip design. To design faster, smaller size, less delay, and low-power algorithm is a very hot research topic.
布局布线是FPGA芯片设计中最耗时的阶段，能够设计出更加快速、更小面积、时延少、低功耗的算法是学术界研究的热点和趋势。
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