Deep Submicron 深次微米 ; 次微米
deep submicron design 深态次微米设计 ; 深能阶瞬时光谱学
deep submicron ic process 深亚微米ic工艺
deep submicron NMOSFET 深亚微米NMOSFET
the deep submicron MOS devices 深亚微米MOS器件
deep submicron ic 深亚微米集成电路
deep submicron vlsi 深亚微米超大规模集成电路
Rapid improvement of chip design techniques and the deep-submicron technology havedriven the embedded system design into System-On-Chip (SoC) era.
芯片设计技术和深亚微米工艺的进步使得系统集成在一块芯片中实现成为可能，嵌入式系统设计进入片上系统芯片时代。
参考来源 - 媒体多处理器系统芯片的设计研究·2,447,543篇论文数据，部分数据来源于NoteExpress
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
With deep submicron technology, crosstalk noise becomes more and more serious.
随着深亚微米技术，串扰噪声问题越来越严重。
In deep submicron era, IC design in physical design has more and more challenge, with the increasing design scale, faster clock frequency and minimizing process dimension.
在深亚微米时代，随着设计规模变大，时钟频率越来越高以及工艺尺寸的减小，IC物理设计面临着诸多困难。
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