Delegates will come together to agree on a core set of transparency principles, data elements, and a reporting framework for good corporate citizens.

FORBES: Nuclear Power Needs Greater Transparency

The Brahma15 is a 21, 000 DMIP Quad-core ARMv7-A instruction set compatible multiprocessor. 32KB instruction and 32KB data caches per processor are backed by a shared 2MB L2 cache and feed the multi-issue, out-of-order superscalar 15-stage plus write back pipeline of the Brahma15.

ENGADGET: Broadcom's new ARM-based chip boosts Ultra HD TV into living rooms of the future