The feature of rapidly develop, high speed and high reliability of Complex Program Logic Device(CPLD) makes CPLD playing a more and more role in the design of digital system.
大规模可编程逻辑阵列（CPLD）的快速开发、在系统编程以及高速可靠的特点使得CPLD在数字系统的构建中起到越来越重要的作用。
Complex program logic device (CPLD) has been chosen as the hardware design platform, driving schedule generator has been described with VHDL.
选用复杂可编程器件(CPLD)作为硬件设计载体，使用VHDL语言对驱动时序发生器进行了硬件描述。
The system utilizes data-chosen-switches, microprocessor AT89C51 and complex logic device (CPLD). The software program is written by C language and VHDL language, respectively.
该系统数字部分主要利用拨码开关、单片机AT89C51，复杂可编程逻辑器件进行设计。
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