Achieve System Clock Timing 实现系统时钟定时
The paper describes the architecture of the clock timing system.
文中详细介绍了此时钟授时系统的系统结构。
A binary tree routing topology is designed for propagating the system clock and trigger signal and the accurate timing and synchronization between sensors are provided by CPLD.
设计了二进制树型拓扑结构传播统一的系统时钟和触发信号,采用CPLD提供传感器间的精确时序和同步。
Absrtact: Along with the increase of digital system working frequency, clock period gets shorter, timing of the system becomes more complex.
摘要:随着数字系统的工作频率的不断提高,时钟周期逐渐变小,而系统时序却越来越复杂。
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