Clock Tree Synthesis 时钟树综合 ; 树合成 ; 时钟树合成 ; 时钟树生成
clock tree balance 时钟树平衡
Clock tree generation 产生时钟树
low power clock tree synthesis 低功耗时钟树综合
Bounded-Skew Clock Tree 有界偏差时钟树
Top Clock tree 顶层时钟树
clock tree layout 时钟布图
In the thesis, we make a deep research on the key technology in ASIC backend design, such as Floorplan, Power-supply distributed design, Clock Tree Synthesis, NanoRouting, Layout Verification.
深入研究了布局规划、电源网络分配、时钟树综合、详细布线以及物理验证等后端设计关键技术。
参考来源 - 基于ASIC实现雷达信号处理芯片的后端设计By using auto placement and routing, the floorplan, clock tree synthesis, placement and routing were achieved. Finally, the asynchronous FIFO of the PCI interface controller was accomplished.
利用自动布局布线工具完成芯片的顶层规划、插入时钟树、布局和布线,最终完成用于PCI接口芯片的异步FIFO设计。
参考来源 - 用于PCI接口芯片的异步FIFO设计·2,447,543篇论文数据，部分数据来源于NoteExpress
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
时钟树的设计是同步数字集成电路设计中的一个重要部分，对系统的性能和可靠性有很大影响。
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