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clock gating

  • 时钟门控：一种在同步时序逻辑电路中使用的定时器信号技术，旨在降低芯片功耗。

网络释义专业释义英英释义

  门控时钟

电子器件投稿系统 关键词： 门控时钟；低功耗；时钟树综合；时钟偏移；IC Compiler [gap=755]Keywords: clock-gating, low power, CTS, clock skew, IC Compiler

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短语

Clock-gating checks 时钟门锁检查 ; 时钟门的检查

clock gating circuit 门控时钟

power and clock gating 功率和时钟门控

fine grain Aggressive Clock Gating 技术包括精细度渐进时钟门控

Programmable clock Gating 可编程门控时钟技术

clock gating technique 门控技术

clock-gating technique 门控技术

Cell level Clock Gating 单元级门控时钟技术

Gating the Clock 选通时钟

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  • 门控时钟 - 引用次数：8

    This paper mainly discussed register clock-gating technique and resolved theproblems that would probably appeared such as design for testability (DFT) problemand timing problem. For RISC processer, clock-gating can reduce power by 18.8%.

    门控时钟技术是一种最常用的低功耗技术,本文着重研究了寄存器门控时钟技术,并对此技术中可能出现的可测性问题和时序问题进行了分析、解决;对于 RISC 微处理器,门控时钟技术可以降低功耗 18.8%。

    参考来源 - 数字集成电路低功耗设计技术的研究及应用

·2,447,543篇论文数据，部分数据来源于NoteExpress

Clock gating

  • abstract: Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree.

以上来源于: WordNet

双语例句

  • In order to reduce the power in the clock tree, a new gating circuit is presented.

    为了能够减少时脉系统的功率消耗，一种新型的闸电路被提出。

    youdao

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