电子器件投稿系统 关键词： 门控时钟；低功耗；时钟树综合；时钟偏移；IC Compiler [gap=755]Keywords: clock-gating, low power, CTS, clock skew, IC Compiler
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Clock-gating checks 时钟门锁检查 ; 时钟门的检查
clock gating circuit 门控时钟
power and clock gating 功率和时钟门控
clock-gating setup and hold 门的建立和保持
fine grain Aggressive Clock Gating 技术包括精细度渐进时钟门控
Programmable clock Gating 可编程门控时钟技术
Globle Clock Gating 全局时钟开关
This paper mainly discussed register clock-gating technique and resolved theproblems that would probably appeared such as design for testability (DFT) problemand timing problem. For RISC processer, clock-gating can reduce power by 18.8%.
门控时钟技术是一种最常用的低功耗技术,本文着重研究了寄存器门控时钟技术,并对此技术中可能出现的可测性问题和时序问题进行了分析、解决;对于 RISC 微处理器,门控时钟技术可以降低功耗 18.8%。
参考来源 - 数字集成电路低功耗设计技术的研究及应用·2,447,543篇论文数据，部分数据来源于NoteExpress
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For RISC processer, clock-gating can reduce power by 18.8%.
对于risc微处理器，门控时钟技术可以降低功耗18.8%。
SMU module adopts the clock-gating method was applied to the survivor path storage block, reduce the survivor path storage memory power dissipation effectively.
在幸存路径管理模块采用门控时钟的方法，有效地降低了对幸存路径存储部分的功耗。
In order to reduce the power in the clock tree, a new gating circuit is presented.
为了能够减少时脉系统的功率消耗，一种新型的闸电路被提出。
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