bus-in signal [计] 总线输入信号
In the section of hardware design, selection of the CAN bus communication interface card, design of CAN nodes and the signal acquisition system are introduced.
在其硬件设计中，着重介绍了CAN总线通讯接口卡的选择、CAN节点设计与信号采集系统设计。
This paper introduces the problems of Signal Integrity in high-speed parallel bus interconnect design and the new design methodology.
本文介绍了高速并行总线互连设计中出现的信号完整性问题及新的设计方法学。
The data transfer rate between varied boards in radar signal processors based on VME or CPCI bus was limited by the bus rate.
在基于VME总线或CPCI总线的雷达信号处理机中，板与板之间的数据传输速率受限于总线的速率。
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