Later, when it becomes necessary to post the modified line to the bus, the whole cache line is written at once.

接着，当需要将修改的线传输给总线时，所有的缓存线会立刻被写入。

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Each pod has its own processors and memory, and is connected to the larger system through a cache-coherent interconnect bus.

每个pod具有自己的处理器和内存，并通过一条高速缓存一致性互连总线(cache - coherent interconnect bus)连接到较大的系统。

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Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.

访问内部统一二级处理器缓存的后端总线接口逻辑。

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The Pentium III is essentially a Pentium II processor, with the same 512KB off-chip secondary cache and 100-MHz system bus.

CNN: Graphics applications scream on Intel Pentium III

When the K7's on-chip 128KB L1 cache becomes too small, the K7 will call on the 200-MHz EV6 bus developed for Digital's Alpha processors.

CNN: AMD's K7: Better than Intel's best processor?