However, there is information embedded in these design artifacts that describe a deeper level of granularity in the board itself: the traces that connect the components on the board.
但是在这些设计文档里面嵌入了一些信息，而这些信息表达了板子更深的粒度信息：板子上连接元件的轨迹。
To resolve them, two design methods of board level dynamic BS chain based on boundary scan technology are proposed in this paper.
为了解决上述问题，文中提出了两种基于边界扫描技术的板级动态链路设计方法。
The IBIS model is used to help get exact information in the integrity constraint design of system board level or multiple board level signals for analysis and calculation.
IBIS模型可以帮助设计者在系统板级或多板信号完整性约束的设计中获取准确的信息，以进行分析和计算。
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