Based on the complex envelope theory, a pre equalizer algorithm and its hardware implementation architecture with FPGA was brought forwards and analyzed.
从信号复包络理论出发，分析并提出了数字电视VS B调制器中预均衡网络的实现算法及其FPGA硬件实现结构。
This paper proposes a kind of optimized TSS algorithm and its implementation based on candidate groups hardware architecture.
提出一种改进的三步搜索算法，并采用基于候选组处理的硬件结构实现。
After the detailed analysis of EBCOT algorithm and pass-parallel coding technique, a dual context window bit-parallel coding method and its architecture for hardware implementation are proposed.
通过研究EBCOT编码原理和通道并行算法的编码过程，提出了双上下文窗口位并行的EBCOT系数位建模方法，详细说明了使用该算法的系数位建模系统的硬件结构。
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