A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
设计了一个数字时钟数据恢复电路,采用相位选择锁相环进行相位调整,在不影响系统噪声性能的前提下大大降低了芯片面积。
That gives them a day or so to adjust their body's clock.
有一天的时间来调整自己身体的生物钟。
This paper adopts a strategy of fitting offset to adjust time, to conquer the impact of network delay and jitter on clock synchronization effectively.
该文提出采用拟合偏差方法进行时钟调整的策略,以有效克服网络延迟和抖动对时钟同步的影响。
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