介绍了在地下漏水探测仪中用CPLD实现高速音频数据采集控制及与单片机的接口逻辑设计。
The gathering and controlling of high speed data of audio frequency by CPLD and the logic design of interface are introduced for underground water leakage detecting instrument.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
文中分析了机群系统中高速通信网卡对PCI接口的要求，采用紧凑设计思想，将网卡的功能逻辑与PCI接口实现在一个FPGA芯片中。
Requirements for high speed network adapter in cluster were analyzed in this thesis. The function logic of the network adapter and PCI interface could be implemented in a single FPGA chip.
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