为了提高时序电路的等价性验证速度，提出一种改进的基于寄存器匹配的验证算法。
An improved algorithm based on register mapping is proposed to increase the speed of equivalence checking for sequential circuits.
与只基于通用割集或专用割集的验证方法相比，该方法可以使组合电路的验证速度明显提高。
Compared with the method only using universal cut or special cut, the method can obviously improve the speed of verification for combinational circuits.
本文对仿真的算法和过程进行了阐述，以混合仿真和等价性验证为基础，提出了加快仿真和验证速度的措施。
This paper expands the algorithm and process of simulation, and then put forward new measures to accelerate it using cc simulation method and equivalence checker.
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