数字逻辑系统的设计离不开计算机辅助设计CAD工具的帮助，尤其是VHDL硬件描述语言。

Now, many digital logic systems cannot do without computer aided design CAD, especially the VHDL Hardware Description Language.

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提出了逻辑函数“系统简化法”的计算机辅助设计方法，从而实现了对多变量逻辑函数的自动简化。

CAD method by using logical function as systematical simplication methods is proposed. The simplication of multivariable logic function is obtained automatically.

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