进行设计采用硬件描述语言
The design is carried out using the hardware description language
以上为机器翻译结果，长、整句建议使用 人工翻译 。
采用模块化设计方法对CPLD进行设计，并给出了硬件描述语言的具体结构。
With blocking means in CPLD design, the structure of HDL (hardware describe language) program is also given.
采用有限状态机设计方法，使用VHDL硬件描述语言编程，并在EDA工具软件平台上进行了仿真和下载。
A design method by usage of finite state machine and VHDL hardware description language to develop the program is adopted, then it is simulated and downloaded on the EDA software platform.
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