每个器件都有一个八位CMOS移位寄存器和CMOS控制电路，八个CMOS数据锁存，八个双极电流吸收达林顿输出驱动器。
Each device has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers.
研究了串行输入，并行输出单向移位寄存器的功能。
The function of the single-direction shift register which is serial input and parallel output is mainly studied.
基于EPP协议的特点，应用复杂可编程逻辑器件(CPLD)开发了移位寄存器输出接口。
Based on the properties of Enhanced Parallel Port (EPP), an interface of shift register output has been developed using Complex Programmable Logic Device (CPLD).
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