关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。

The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.

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延迟电路可通用于输出时钟的频率调整以及相位调整这两方面。

The delay circuit is used for both frequency and phase adjustments of the output clock.

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论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。

And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.

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