第三章介绍高速误码率测试仪发端子系统的设计方案；
The third chapter discusses transmitter' s de-sign scheme of high speed BERT.
简述了FPGA在高速位误码率测试仪中的应用，对误码率测试仪的结构，及其FPGA实现进行了详细的介绍。
The structure of the high-speed BER testing instrument is introduced. The application of FPGA in the instrument and the realization of FPGA are expounded.
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