CPU内核采用VHDL硬件描述语言输入，结合流行的EDA设计、综合、仿真工具，最后在FPGA上实现该内核。
The reference CPU core use VHDL language input, make logic synthesis and simulation through the popular EDA tools, then it was implemented in FPGA.
该设计采用可编程逻辑器件，VHDL硬件描述语言为输入工具，接口简单，可靠性高，具有一定的实用价值。
The programmable logic device and VHDL is used as input tools, which have simple software interface, good reliability and practical value.
该设计采用可编程逻辑器件，ABEL HDL硬件描述语言为输入工具，接口简单，可靠性高，具有一定的实用价值。
The programmable logic device and ABEL-HDL is used as input tools, which have simple software interface, good reliability and practical value.
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