... 触发脉冲锐化电路 trigger sharpener 触发脉冲信号 window signal 触发脉冲形成器 trigger shaper ...
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使用了FPGA进行触发脉冲信号的调制，提高直流调速系统的性能及稳定性。
FPGA is used to modulate spring pulse signal so as to improve the capability and stability of the DC timing system.
水平失真触发：当信号变高或者变低，并保持此状态超过指定时间时触发。这是很有用的对于脉冲串的末端触发。
Level dropout: This detects an edge followed by a specified time with no edges. It is useful for triggering on the end of a pulse train.
当接收到短脉冲检测开始触发信号时，向自动增益控制放大器(201)输出一个增益控制信号，以便用最大值进行放大。
Upon reception of a burst detection start trigger signal, a gain control signal is output to an automatic gain control amplifier (201) so as to perform amplification with a maximum value.
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