将磁心存储器读出放大器的输出选通到寄存器的触发器中的一种脉冲。
A pulse to gate the output of a core memory sense amplifier into a trigger in a register.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
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