差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。

The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.

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设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。

A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.

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