For digital integrated circuit, the behavioral modeling of one DDS system which is based on the pipeline, is used as an example. The application of Verilog hardware design language in the macromodel construction is presented.
针对数字集成电路的宏模型,本文以一个基于流水线的DDS系统行为级建模为实例,阐述了Verilog硬件设计语言在建立集成电路宏模型中的应用。
参考来源 - 集成电路宏模型的研究与构建·2,447,543篇论文数据，部分数据来源于NoteExpress
提出了一种全新的电荷泵锁相环的行为级建模方法。
A novel multi-layer Charge-Pump Phase-Locked Loop (CP-PLL) behavioral model is presented in this paper.
UML活动图可以表示不同抽象级的控制流，很适合用于对系统的行为建模。
UML activity diagrams can be used to describe the control flow of different abstract levels and are very suitable for modeling system behaviors.
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