按照该方案设计的虚拟逻辑分析仪实现了大数据量采集与快速传输。
The victual logic analyzer which is designed according to these techniques can transfer mass data rapidly.
本文介绍了一种基于FPGA的USB2.0高速、低成本的虚拟逻辑分析仪的设计原理与实现方法。
This paper introduces the design and realization of a high-speed and low-cost virtual logic analyzer based on FPGA and USB2.0 bus.
正是基于此,本文充分运用FPGA技术和虚拟仪器技术,开展了虚拟逻辑分析仪系统的研究与设计。
On the basis of above mentioned, this thesis discusses the research and design of virtual logic analyzer based on the full use of FPGA technology and virtual instrument technology.
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