从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计。
The design of chip test controller of a security chip and design for test of corresponding cores are discussed in detail.
本文首次将测试调度问题与芯片级测试控制器设计问题结合起来，提出了一种能够灵活实现各种测试调度结果的芯片级测试控制器设计。
A kind of chip-level test controller which can flexibly carry out the result of test scheduling is presented, which also takes chip test scheduling into account.
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