时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。

Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.

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固定频率源可以在在通讯系统和雷达系统中作为本机振荡器，也可以作为数字电路的基准时钟信号，因此得到了广泛的应用。

Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive-applied technique.

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不接受带有参考线频率的时钟的系统。

Systems with line frequency referred clocks not acceptable .

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