采用流水线结构的硬件实现表明，新算法占用的资源大约为原来的1/16。

The pipelined implementation shows that the new algorithm occupies about 1/16 of the old one.

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核心模块快速傅立叶逆变换（IFFT）采用基于16位定点运算的基-2时间抽取算法和流水线结构。

The radix-2 decimation-in-time algorithm based on 16-bit fixed-point operation and pipeline architecture are adopted in the core module IFFT(Inverse Fast Fourier Transform).

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该芯片采用了改进的直接数字频率合成算法、流水线结构与ROM分时复用技术，保证了芯片的高性能和速度，节省了芯片面积。

A modified direct digital frequency synthesis (DDS), pipelined structure, and time-sharing ROM are adopted in the chip, for saving chip area and ensuring high performance and speed.

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