针对DSP片内资源特点设计了片内存储器数据分配方案，并根据该方案优化了MPEG 4视频压缩的数据流模式。
The data flow scheme of the MPEG-4 video compression is optimized by utilizing the DSP's on-chip memory.
利用FPGA在硬件上实现了该算法，内部采用流水线技术，校正系数存储在FPGA的片内存储器中并实现了盲元补偿。
In the FPGA design, the pipelined technique is applied and the correction coefficient is stored in the interior memory of FPGA, meanwhile, blind pixel compensation is implemented.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
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