组单元的模块化设计结构与流水线设计技术使得硬件逻辑资源得到更有效的利用。
With the modularization design and pipeline technology, this architecture makes more efficient using of hardware resources.
该方案利用DCT的行列分离特性，采用流水线设计技术，将二维DCT/IDCT实现转化为两个一维DCT/IDCT实现。
The way adopted pipeline architecture and changed 2-D DCT/IDCT to two 1-D DCT/IDCT based on characteristic of row-column decomposition.
本设计为兼顾模数转换器的速度和精度，采用数字校正技术，以每级1.5 位的9 级流水线结构实现。
The converter has a good tradeoff between conversion speed and conversion precision. It is a 1.5-bit per stage with 9 stage and digital correction technique.
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