... gate land || 浇口面 gate leakage current || 栅极漏电流 gate level simulator || 门级模拟程序 ...
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Secondly, considering the design parameters including the subthreshold leakage current, gate leakage current, active power and speed, two new sub 65 nm domino techniques are proposed.
其次,在权衡考虑动态功耗、亚阈值漏电流、栅极漏电流和速度等多个重要指标后,设计了两种新型的多米诺或门结构。
参考来源 - 亚65纳米CMOS工艺低功耗高性能多米诺电路的设计研究·2,447,543篇论文数据，部分数据来源于NoteExpress
各种MOSFET测试都要求进行弱电流的测量。这些测试包括栅极漏电、泄漏电流与温度的关系、衬底对漏极的漏电和亚阈区电流等。
Various MOSFET tests require making low current measurements. Some of these tests include gate leakage, leakage current vs. temperature, substrate to-drain leakage, and sub-threshold current.
输出功率和漏电流增加的栅极电压的增加。
The output power and drain current increase as the gate voltage increases.
随着周围2.5 V的栅极电压(最低)，输出功率和漏电流增加了很多。
With a gate voltage around 2.5v (minimum), output power and drain current increases substantially.
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