提出了一种展频时钟生成的方法，使用MATLAB和SIMULINK开发出了快速模拟基于分数N型频率合成器的展频时钟生成器的环境。
A fast simulation environment has been developed using MATLAB and SIMULINK for behavioral level simulation of spread spectrum clock generator based Fractional-N frequency synthesizers.
然后，它生成一个报告，列出这些代码单元每个获得了多少个“节拍(tick)”(即当代码的特定单元正在运行时发生了多少次系统时钟中断)。
Then it generates a report that lists how many "ticks" each of these units of code received (how many times a system-clock interrupt occurred when that particular unit of code was running).
在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse.
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