...件 布局、器件放置(Placement) 当模块宏观的位置确定后,就在相应的区域内放置标准单元级的电路 时钟树综合(Clock Tree Synthesis) 为了满足时序收敛的要求(Timing Closure),保证每个模块及每个 寄存器的时钟输入的相位误差最小,必须在时钟源到寄存器最短的通 路...
基于100个网页-相关网页
低功耗时钟树综合 low power clock tree synthesis
·2,447,543篇论文数据，部分数据来源于NoteExpress
本论文对时钟树综合中的几个最关键问题进行深入研究。
And the clock tree synthesis is the most critical factor in timing closure.
芯片测试结果的正确也验证了这种时钟树综合方案的有效性。
The correct test results of the chip also verify the effectiveness of this clock tree synthesis program.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
应用推荐