采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
所述数字示波器信号等效采样方法利用两路相反的采样时钟进行采样，有效的消除了隆起现象和毛刺现象。
In the digital oscilloscope signal equivalent sampling method, a sampling clock with two inverse ways is utilized for sampling, thereby effectively eliminating the phenomena of uplift and burr.
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