逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。

Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.

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处理器包含一个时钟，一条指令控制单元，一个算术和逻辑单元，并登记。

The processor contains a clock, an instruction control unit, an arithmetic and logic unit, and registers.

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整个设计采用VHDL语言描述，经过逻辑优化，该显示控制器有着比同类控制器占用资源少、时钟延迟小等优点。

The whole design is described in VHDL. By logic optimization, the controller has an advantage of less resource utilization and less clock delay compared with other similar controllers.

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