本文提出了逻辑法设计时序控制电路的改进方法。
An improvement of logic design approach for time-sequence control circuit is presented.
PLC编程技术包括：经验设计法，逻辑设计法、时序图设计法、顺序控制设计法等编程方法。
PLC programming technique includes experience design method, logic design method, cycle diagram design method and sequential control design method.
CPLD的接口时序逻辑控制功能采用状态机工作方式实现，并给出了用VHDL编写的主要源代码。
State- machine is used to implement the timing logic in CPLD, and the main codes written by VHDL language are given.
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